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SP7514 and HS3140
Corporation
SIGNAL PROCESSING EXCELLENCE
14-Bit Multiplying DACs
s Monolithic Construction s 14-Bit Resolution s 0.003% Non-Linearity s Four-Quadrant Multiplication s Latch-up Protected s Low Power - 30mW s Single +15V Power Supply
DESCRIPTION... The SP7514 and HS3140 are precision 14-bit multiplying DACs, that provide four-quadrant multiplication. Both parts accept both AC and DC reference voltages. The SP7514 is available for use in commercial and industrial temperature ranges, packaged in a 20-pin SOIC. The HS3140 is available in commercial and military temperature ranges, packaged in a 20-pin side-brazed DIP.
V REF
19 96k
15 EQUAL SECTIONS 96k
48k 96k
SP7514, HS3140 SP7514
2 96k I OUT2
GND VDD
3 18 4 to 16 DECODE 4 5 6 7 BIT 4 17 BIT 14 LSB 6k 20 R FEEDBACK SWITCHES ARE SHOWN IN THE HIGH STATE 1 I OUT1
BIT 1 BIT 2 BIT 3 (MSB)
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SPECIFICATIONS
(Typical @ 25C, nominal power supply, VREF = +10V, unipolar unless otherwise noted)
PARAMETER DIGITAL INPUT Resolution 2-Quad, Unipolar Coding 4-Quad, Bipolar Coding Logic Compatibility Input Current REFERENCE INPUT Voltage Range Input Impedance ANALOG OUTPUT Scale Factor Scale Factor Accuracy Output Leakage Output Capacitance COUT 1, all inputs high COUT 1, all inputs low COUT 2, all inputs high COUT 2, all inputs low STATIC PERFORMANCE Integral Linearity SP7514KN/BN, HS3140-4 SP7514JN/AN, HS3140-3 Differential Linearity SP7514KN/BN, HS3140-4 SP7514JN/AN, HS3140-3 Monotonicity SP7514KN/BN, HS3140-4 SP7514JN/AN, HS3140-3 STABILITY Scale Factor Integral Linearity Differential Linearity Monotonicity Temp. Range SP7514JN/KN, HS3140C SP7514AN/BN HS3140B DYNAMIC PERFORMANCE Digital Small Signal Settling Digital Full Scale Settling Reference Feedthrough Error @ 1kHz @ 10kHz Reference Input Bandwidth POWER SUPPLY (VDD) Operating Voltage Voltage Range Current Rejection Ratio
MIN. 14
TYP.
MAX.
UNITS Bits
CONDITIONS
Binary Offset Binary CMOS, TTL
1 25 9.75 225 1 10
A V KOhms A/VREF % nA pF pF pF pF
Note 1
Note 2
3.25 75
Note 3 Note 4
100 50 50 100
0.003 0.006 0.003 0.006
0.006 0.012 0.006 0.012
Note 5 % FSR % FSR Note 6 %FSR % FSR
Guaranteed to 14 bits Guaranteed to 13 bits 4 0.5 0.5 0 -40 -55 1.0 2.0 200 2 1 +15 5% +8 0.005 +18 2.0 ppm FSR/C ppm FSR/C ppm FSR/C C C C S S V mV MHz V V mA %/% (VREF = 20Vpp) (TMIN to TMAX) Note 7 and 8
1.0 1.0 +70 +85 +125
Note 9
160
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SIGNAL PROCESSING EXCELLENCE
SPECIFICATIONS (continued)
(Typical @ 25C, nominal power supply, VREF = +10V, unipolar unless otherwise noted)
PARAMETER MIN. TYP. MAX. ENVIRONMENTAL AND MECHANICAL Operating Temperature SP7514JN/KN 0 +70 SP7514AN/BN -40 +85 HS3140-C 0 +70 HS3140-B -55 +125 HS3140-B/883 -55 +125 Storage Temperature -65 +150 Package SP7514_N 20-pin SOIC HS3140 20-pin Side-Brazed DIP
UNITS
CONDITIONS
C C C C C C
Notes: 1. Digital input voltage must not exceed supply voltage or go below -0.5V ; "0" <0.8V; 2.4V < "1" VDD. 2. AC or DC; use R6758-1 for fixed reference applications 3. Using the internal feedback resistor and an external op amp. The Scale Factor can be adjusted externally by variable resistors in series with the reference input and/or in series to the internal feedback resistor. Please refer to the Applications Information section. 4. At 25C; the output leakage current will create an offset voltage at the external op amps output. It doubles every 10C temperature increase. 5. Integral Linearity is measured as the arithmetic mean value of the magnitudes of the greatest positive deviation and the greatest negative deviation from the theoretical value for any given input combination. 6. Differential Linearity is the deviation of an output step form the theoretical value of 1LSB for any two adjacent digital input codes. 7. At 25C, the output leakage current will create an offset voltage output. It doubles every 10C temperature increase. 8. Using the internal feedback resistor and an external op amp. 9. Use series 470ohm resistor to limit start-up current.
CHARACTERISTIC CURVES
(Typical @ + 25C, VDD = + 15VDC, VREF = + 10VDC, unless otherwise noted)
INTEGRAL LINEARITY ERROR - %
0.048
50
LINEARITY ERROR - PPM
40
30
2 LSB
0.024
20 1 LSB 10
0.012 0.006 0.003 0.01 0.1 V REF -VOLTS 1 10
1/2 LSB @ 16 BITS
Integral Linearity Error vs. Reference Voltage
0.048%
0 0 10 20 30 VOS-mV 40 50
LINEARITY - %
Additional Linearity Error vs. Output-Amplifier Offset-Voltage (VREF = + 10V)
0.024%
0.01
0.012% 0.006% 0.003% 4 6 8 10 12 14 16 18
0.008
GAIN CHANGE - %
V DD -VOLTS
0.006
Linearity vs. Supply Voltage
2.5
0.004
2.0
0.002
I DD -mA
1.5
0 4 6 8 10 12 14 16 18 VDD -VOLTS
1.0 4 6 8 10 12 14 16 18 10 VDD -VOLTS
Gain Change vs. Supply Voltage Power Supply Current vs. Voltage
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PIN ASSIGNMENTS... Pin 1 - IO1 - Current Output 1. Pin 2 - IO2 - Current Output 2. Pin 3 - GND - Ground. Pin 4 - DB13 - MSB, Data Bit 1. Pin 5 - DB12 - Data Bit 2. Pin 6 - DB11 - Data Bit 3. Pin 7 - DB10 - Data Bit 4. Pin 8 - DB9 - Data Bit 5. Pin 9 - DB8 - Data Bit 6. Pin 10 - DB7 - Data Bit 7. Pin 11 - DB6 - Data Bit 8. Pin 12 - DB5 - Data Bit 9. Pin 13 - DB4 - Data Bit 10. Pin 14 - DB3 - Data Bit 11. Pin 15 - DB2 - Data Bit 12. Pin 16 - DB1 - Data Bit 13. Pin 17 - DB0 - LSB, Data Bit 14. Pin 18 - VDD - Positive Supply Voltage. Pin 19 - VREF - Reference Voltage Input. Pin 20 - RFB - Feedback Resistor.
PRINCIPLES OF OPERATION The SP7514/HS3140 achieve high accuracy by using a decoded or segmented DAC scheme to implement this function. The following is a brief description of this approach. The most common technique for building a D/A converter of n bits is to use n switches to turn n current or voltage sources on or off. The n switches and n sources are designed so that each switch or bit contributes twice as much to the D/A converter's output as the preceding bit. This technique is commonly known as binary weighting and allows an n-bit converter to generate 2n output levels by turning on the proper combination of bits. In such binary-weighted converter, the switch with the smallest contribution (the LSB) accounts for only 2-n of the converter's full-scale value. Similarly, the switch with the largest contribution (the MSB) accounts for 2 -1 or half of the converter's full-scale output. Thus it is easy to see that a given percent change in the MSB will have a greater effect on the converter's output than would a similar percent change in the LSB. For example, a 1% change in the LSB of a 10 bit converter would only affect the output by 0.001% of full-scale. A 1% change in the MSB of the same converter would affect the output by 0.5% of FSR. In order to overcome the problem which results from the large weighting of the MSB, the two MSB's can be decoded to three equally weighted sources. Table 1 shows that all combinations of the two MSB's of a converter result in four output levels. So by replacing the two MSB's with three bits equally weighted at 1/ 4 full-scale and decoding the two MSB digital inputs into three lines which drive the equally weighted bits, the same functional performance can be obtained. Thus by replacing the two MSB switches of a conventional converter with three switches properly decoded, the contribution of any switch is reduced from 1/2 to 1/4. This reduction in sensitivity also reduces the
FEATURES... The SP7514 and HS3140 are precision 14-bit multiplying DACs. The DACs are implemented as a onechip CMOS circuit with a resistor ladder network. Three output lines are provided on the DACs to allow unipolar and bipolar output connection with a minimum of external components. The feedback resistor is internal. The resistor ladder network termination is externally available, thus eliminating an external resistor for the 1 LSB offset in bipolar mode. The SP7514 is available for use in commercial and industrial temperature ranges, packaged in a 20-pin SOIC. The HS3140 is available in commercial and military temperature ranges, packaged in a 20-pin side-brazed DIP. For product processed and screened to the requirements of MIL-M- 38510 and MIL-STD-883C, please consult the factory (HS3140B only). 162
Cf Rf VREF Ri CO Rp C
- +
EO
Figure 1. SP7514/HS3140 Equivalent Output Circuit
Corporation
SIGNAL PROCESSING EXCELLENCE
2 - 1(MSB) 0 0 1 1
2
-2
Output 0 1/4 Full-Scale 1/2 Full-Scale 3/4 Full-Scale
V REF
400
470 V DD 200 RFEEDBACK I O1 R OS A + V OUT
0 1 0 1
Table 1. Contribution of the two MSB's
DIGITAL INPUTS
SP7514 HS3140
I O2
accuracy required of any switch for a given overall converter accuracy. With the decoded converter described above, a 1% change in any of the converter's switches will affect the output by no more than 0.25% of full-scale as compared to 0.5% for a conventional converter. In other words the conventional D/A converter can be made less sensitive to the quality of its individual bits by decoding. In the SP7514/HS3140 the first four MSB's are decoded into 16 levels which drive 15 equally weighted current sources. The sensitivity of each switch on the output is reduced by a factor of 8. Each of the 15 sources contributes 6.25% output change rather than an MSB change of 50% for the common approach. Following the decoded section of the DAC a standard binary weighted R-2R approach is used. This divides each of the 16 levels (or 6.25% of F.S.) into 4096 discrete levels (the 12 LSB's). Output Capacitance The SP7514/HS3140 have very low output capacitance (CO). This is specified both with all switches ON and all switches OFF. Output capacitance varies from 50pF to 100pF over all input codes. This low capacitance is due in part to the decoding technique used. Smaller switches are used with resulting less capacitance. Three important system characteristics are affected by CO and CO; namely digital feedthrough, TRANSFER FUNCTION (N=14)
BINARY INPUT UNIPOLAR OUTPUT BIPOLAR OUTPUT 111...111 100...001 100...000 011...111 000...001 000...000 -VREF (1 - 2-N) -VREF (1/2 + 2 )
-N
GND
Figure 2. Unipolar Operation
settling time, and bandwidth. The DAC output equivalent circuit can be represented as shown in Figure 1. Digital feedthrough is the change in analog output due to the toggling conditions on the converter input data lines when the analog input VREF is at 0V. The SP7514/HS3140 very low CO and therefore will yield low digital feedthrough. Inputs to the DAC can be buffered. This input latch with microprocessor control is shown in Figure 4. Settling time is directly affected by CO. In Figure 1, CO combines with Rf to add a pole to the open loop response, reducing bandwidth and causing excessive phase shift - which could result in ringing and/or oscillation. A feedback capacitor, Cf must be added to restore stability. Even with Cf, there is still a zero-pole mismatch due to RiCO which is code dependent. This code dependent mismatch is minimized when CORi = RfCf. However Cf must now be made larger to compensate for worst case RiCO - resulting in reduced bandwidth and increased settling time. With the SP7514/HS3140, small values for Cf must be used.
400 V REF 470 V DD 200 R FEEDBACK I O1 DIGITAL INPUTS R OS1 A1 + 4K 4K I O2 R OS2 GND R OS2 A2 + R
SP7514 HS3140
V OUT
-VREF (1 - 2 -(N - 1)) -VREF (2 0 VREF (2 -(N - 1)) VREF (1 - 2 -(N - 1)) VREF
-(N - 1)
)
-VREF /2 -VREF (1/2 - 2-N) -VREF (2 0
(N - 1)
)
V OUT1 A1, A2 , OP-07
Table 2. Transfer Function
Figure 3. Bipolar Operation
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SIGNAL PROCESSING EXCELLENCE
VREF (+ 25V MAX) D0 D1 D2 D3 D4 D5 D6 D7 CLK D0 D1 D2 D3 D4 D5 D6 D7
V DD 400 LSB VREF 15 + VDD 14 13 12 11 10 9 I 01 I 02 2 RF VOUT 0 TO - V REF (1-2 - N) 200 470 3 UNIPOLAR MODE (2-QUADRANT)
74273
A 3 +1
-
6
D0 D1 D2 WR G2A 74LS138 BDSEL A2 A1 A0 G2B C B A LATCHES CLK D3 D4 D5 D6 D7
SP7514/ SP7514/ 7516 HS3140
8 7 6 5 4 3 2 MSB GND
R 0S
74273
1. Using LF441A amplifier (low power - 741 pinout) 2. Specified offset: 0.5mV max 3. Temperature coefficient of input offset: 10V/C max VOS max (0C to 70C) = 0.5mV + (70V)10 = 1.2mV Add'l nonlinearity (max.) = 1.2mV x 0.065mV/mV = 78V (1/2 LSB @ 16 Bits) Where: 78V = 1/2 LSB @ 16 Bits (10V range)
ADDRESS DECODER
Figure 4. Microprocessor Interface to SP7514/HS3140
Resistor Rp can be added, this will parallel Rj decreasing the effective resistance. If Cf is reduced the bandwidth will be increased and settling time decreased. However a system penalty for lowering Cf is to increase noise gain. The trade-off is noise vs. settling time. If Rp is added then a large value (1F or greater) non-polarized capacitor Cp should be added in series with Rp to eliminate any DC drifts. If settling time is not important, eliminate Rp and Cp, and adjust Cf to prevent overshoot. Output Offset In most applications, the output of the DAC is fed into an amplifier to convert the DAC's current output to voltage. A little known and not commonly discussed parameter is the linearity error versus offset voltage of the output amplifier. All CMOS DAC's must operate into a virtual ground, i.e., the summing junction of an op amp. Any amplifier's offset from the amplifier will appear as an error at the output (which can be related to LSB's of error). Most all CMOS DAC's currently available are implemented using an R-2R ladder network. The formula for nonlinearity is typically 0.67mV/mVOS (not derived here). However the SP7516 has a coefficient of only 0.065mV/mVOS. This is due to the decoding technique described earlier. CMOS DAC applications notes (including this one) always show a potentiometer used to null out the amplifier's offset. If an amplifier is chosen having `pretrimmed' offset it may be possible to eliminate this component. Consider the following calculations:
Via the above configuration, the SP7514/HS3140 can be used to divide an analog signal by digital code (i.e. for digitally controlled gain). The transfer function is given in Table 2, where the value of each bit is 0 or 1. Division by all "0"s is undefined and causes the op amp to saturate. Applications Information Unipolar Operation Figure 2 shows the interconnections for unipolar operation. Connect IO1 and FB1 as shown in diagram. Tie IO2 (Pin 7), FB3 (Pin 3), and FB4 (Pin 1) to Ground (Pin 8). As shown, a series resistor is recommended in the VDD supply line to limit current during `turn-on'. To maintain specified linearity, external amplifiers must be zeroed. Apply an ALL "ZEROES" digital input and adjust ROS for VOUT = 0 1mV. The SP7514 and HS3140 have been used successfully with OP-07, OP-27 and LF441A. For high speed applications the SP2525 is recommended. Bipolar Operation Figure 3 shows the interconnections for bipolar operation. Connect IO1, IO2, FB1, FB3, FB4 as shown in diagram. Tie LDTR to IO2. As shown, a series resistor is recommended in the VDD supply line to limit current during `turn-on. To maintain specified linearity, external amplifiers must be zeroed. This is best done with VREF set to zero and, the DAC register loaded with 10...0 (MSB = 1). Set R0S1 for V01 = 0. Set R0S2 for VOUT = 0. Set VREF to +10V and adjust RB for VOUT to be 0V. Grounding Connect all GND pins to system analog ground and tie this to digital ground. All unused input pins must be grounded.
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SIGNAL PROCESSING EXCELLENCE
ORDERING INFORMATION
Model ................................................................ Monotonicity .................................. Temperature Range .................................... Package Double-Buffered 12-Bit Multiplying DAC HS3140C-3Q ............................................................ 13-Bit ............................................... 0C to +70C ................... 20-pin, 0.3" Side-Brazed HS3140B-3Q ............................................................ 13-Bit ......................................... -55C to +125C ................... 20-pin, 0.3" Side-Brazed HS3140B-3/883 ....................................................... 13-Bit ......................................... -55C to +125C ................... 20-pin, 0.3" Side-Brazed HS3140C-4Q ............................................................ 14-Bit ............................................... 0C to +70C ................... 20-pin, 0.3" Side-Brazed HS3140B-4Q ............................................................ 14-Bit ......................................... -55C to +125C ................... 20-pin, 0.3" Side-Brazed HS3140B-4/883 ....................................................... 14-Bit ......................................... -55C to +125C ................... 20-pin, 0.3" Side-Brazed SP7514JN ................................................................ SP7514KN ............................................................... SP7514AN ............................................................... SP7514BN ............................................................... 13-Bit ............................................... 0C 14-Bit ............................................... 0C 13-Bit .......................................... -40C 14-Bit .......................................... -40C to to to to +70C +70C +85C +85C ...................................... 20-pin, ...................................... 20-pin, ...................................... 20-pin, ...................................... 20-pin, 0.3" 0.3" 0.3" 0.3" DIP DIP DIP DIP DIP DIP
SOIC SOIC SOIC SOIC
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